| Type |
D-Type |
| Latch Mode |
Transparent |
| Bus Hold |
No |
| Logic Family |
HC |
| Process Technology |
CMOS |
| Number of Elements per Chip |
1 |
| Number of Channels per Chip |
8 |
| Number of Inputs per Chip |
8 |
| Number of Outputs per Chip |
8 |
| Number of Output Enables per Element |
1 |
| Number of Input Enables per Element |
1 |
| Number of Selection Inputs per Element |
0 |
| Output Type |
3-State |
| Polarity |
Non-Inverting |
| Set/Reset |
No |
| Minimum Operating Supply Voltage (V) |
2 |
| Maximum Operating Supply Voltage (V) |
6 |
| Typical Operating Supply Voltage (V) |
5 |
| Minimum Operating Temperature (°C) |
-40 |
| Maximum Operating Temperature (°C) |
85 |
| Minimum Storage Temperature (°C) |
-65 |
| Maximum Storage Temperature (°C) |
150 |
| Maximum Propagation Delay Time @ Maximum CL (ns) |
200@2V|40@4.5V|34@6V |
| Absolute Propagation Delay Time (ns) |
285 |
| Propagation Delay Test Condition (pF) |
150 |
| Maximum High Level Output Current (mA) |
-7.8 |
| Maximum Low Level Output Current (mA) |
7.8 |
| Maximum Quiescent Current (uA) |
8 |
